تحلیل و طراحی سنتزکننده فرکانس برپایه ساختارحلقه قفل فاز نوع سوم برای سیستم های رادار موج پیوسته با مدولاسیون فرکانس

نوع مقاله : مقاله پژوهشی

نویسندگان

1 دانشکده مهندسی برق و کامپیوتر، دانشگاه تربیت مدرس، تهران، ایران

2 تربیت مدرس

چکیده

در این مقاله، پیشنهاد به کارگیری حلقه قفل فاز نوع سوم در سنتزکننده های فرکانس عدد کسری برای سیستم رادار موج پیوسته با مدولاسیون فرکانس مطرح می شود. تحلیل حلقه قفل فاز نوع سوم و مقایسه آن با حلقه قفل فاز متداول نوع دوم نشان می دهد که این ساختار تغییرات فرکانس خطی در سیستم رادار موج پیوسته را با دقت بیشتری دنبال می کند و خطای فاز ماندگار در آن، برخلاف حلقه قفل فاز نوع دوم، به طور مستقل از پهنای باند حلقه و یا شیب تغییرات فرکانس خروجی، به صفر می رسد. با توجه به شرایط پایداری، توان مصرفی، نویز فاز خروجی و دقت مورد نیاز برای مدولاسیون فرکانس، روند طراحی سنتزکننده فرکانس مبتنی بر حلقه قفل فاز نوع سوم در این مقاله بیان شده و برمبنای آن، یک سنتزکننده فرکانس عدد کسری به همراه مدولاتور دلتا- سیگما جهت اعمال مدولاسیون مثلثی در فرکانس مرکزی 10 گیگاهرتز با شیب تغییرات فرکانس 2 مگاهرتز بر میکروثانیه طراحی می شود. شبیه سازی مدار طراحی شده در فناوری 0.18 میکرومتر سی ماس، کاهش 34 درصدی خطای فرکانس خروجی را نسبت به طراحی با ساختار حلقه قفل فاز نوع دوم، در توان مصرفی یکسان، نشان می دهد.

کلیدواژه‌ها

موضوعات

عنوان مقاله [English]

Analysis and Design of a Type-III PLL-based Frequency Synthesizer for FMCW Radar Applications

نویسندگان [English]

  • Ali Alaee Salavat 1
  • Saeed Saeedi 2
1 Faculty of Electrical and Computer Engineering, Tarbiat Modares University, Tehran, Iran
2 Faculty of Electrical and Computer Engineering, Tarbiat Modares University, Tehran, Iran
چکیده [English]

In this paper, a fractional-N frequency synthesizer based on type-III phase locked loop (PLL) architecture is proposed for frequency modulated continuous wave (FMCW) radar systems. Analysis of the type-III PLL shows that it generates linear frequency ramps more accurately compared with its type-II counterpart and its steady-state phase error is zero, independent of the loop bandwidth and rate of the frequency variation. Considering the stability issues, power consumption, output phase noise and accuracy of the frequency ramp generation, design procedure of the type-III FMCW frequency synthesizer is presented in this paper. Based on this procedure, a fractional-N frequency synthesizer, which generates the triangular frequency sweep by a delta-sigma modulator, is designed at the center frequency of 10 GHz with frequency variation rate of 2 MHz/µs. Simulation results of the circuit, designed in a 0.18µm CMOS technology, illustrates that the frequency error is reduced by about 34% compared to the type-II PLL, designed at the same power consumption.

کلیدواژه‌ها [English]

  • Frequency modulated continuous wave (FMCW) radar
  • Fractional-N frequency synthesizer
  • Type-III phase locked loop (PLL)
  • Loop filter
  • Delta-sigma modulator

مراجع

[1] J. Vovnoboy, et al., “A Dual-Loop Synthesizer With Fast Frequency Modulation Ability for 77/79 GHz FMCW Automotive Radar Applications,” IEEE J. of Solid-State Circuits, vol. 53, no.5, pp. 1328 - 1337, May 2018.
[2] H. Chen and L. Lu, “A 34.8%-PAE CMOS Transmitter Frontend for 24-GHz FMCW Radar Applications” IEEE Asian Solid-State Circuits Conference, pp. 265-268, Nov. 2012.
[3] W. Wu, R. Staszewski and J. Long, “A 56.4- to-63.4 GHz Multi-Rate All-Digital Fractional- N PLL for FMCW Radar Applications in 65 nm CMOS” IEEE J. of Solid-State Circuits, vol. 49, no. 5, pp. 1081-1096, May 2014.
[4] J. Kielb and M. Pulkrabek, “Application of a 15 GHz FMCW radar for industrial control and process level measurement” IEEE MTT-S Digest, pp. 281- 284, 1999.
[5] Y. Im, J. Lee and S. Park, “A DDS and PLLbased X-band FMCW radar system,” IEEE MTT-S International Microwave Workshop Series on Intelligent Radio for Future Personal Terminals, 2011.
[6] S. Liu, Y. Zheng and X. He., “Design of a wideband low power FMCW synthesizer in 65 nm CMOS for radar applications,” IEEE International Symposium on Circuits and Systems (ISCAS), pp.1776-1779, 2014.
[7] F. Herzel, A. Ergintav and Y. Sun, “Phase Noise Modeling for Integrated PLLs in FMCW Radar,” IEEE Transactions on Circuits and Systems-II: Express Briefs, vol. 60, no.3, pp.137 - 141, March 2013.
[8] M. Dayanik and M. Flynn, “Digital Fractional- N PLLs Based on a Continuous-Time Third- Order Noise-Shaping Time-to-Digital Converter for a 240-GHz FMCW Radar System,” IEEE J. of Solid-State Circuits, vol. 53, no.6, pp. 1719 -1730, June 2018.
[9] F. Herzel, D. Kissinger and H. Jalli Ng, “Analysis of Ranging Precision in an FMCW Radar Measurement Using a Phase-Locked Loop,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 2, pp. 783-792, Feb. 2018.
[10] T. Mitomo, et al., “A 77 GHz 90 nm CMOSTransceiver for FMCW Radar Applications,” IEEE J. of Solid-State Circuits, vol. 45, no.4, pp. 928 - 937, April 2010.
[11] J. Lee, et al., “A Fully-Integrated 77-GHz FMCW Radar Transceiver in 65-nm CMOS Technology” IEEE J. of Solid-State Circuits, vol. 45, no. 12, pp. 2746-2756, Dec. 2010.
[12] T. Luo, C. Wu and Y. Chen, “A 77-GHz CMOS FMCW Frequency Synthesizer With Reconfigurable Chirps,” IEEE Transactions on Microwave Theory and Techniques, vol. 61, no. 7, pp. 2641-2647, July 2013.
[13] A. Sai, et al., “A Digitally Stabilized Type-III PLL Using Ring VCO with 1.01 psrms Integrated Jitter in 65nm CMOS,” IEEE International Solid State Circuits Conference, ISSCC, pp. 248-249, 2012.
[14] H. Adrang and H. Miar Naeimi, “A type III fast locking time PLL with transconductor-C structure,” IEEE International Midwest Symposium on Circuits and Systems, 2009.
[15] S. Golestan, et al., “Advantages and Challenges of a Type-3 PLL,” IEEE Transactions on Power Electronics, vol. 28, no.11, pp. 4985 - 4997, Nov. 2013.
[16] H. Rategh, H. Samavati and T. Lee., “A CMOS Frequency Synthesizer with an Injection-Locked Frequency Divider for a 5- GHz Wireless LAN Receiver,” IEEE J. of Solid-State Circuits, vol. 35, no.5, pp.780-787, May 2000.
[17] B. Razavi, “RF Microelectronics,” 2nd ed., Prentice Hall, New York, 2012. [18] M. Perrott, M. Trott and C. Sodini, “A modeling approach for ΣΔ fractional-N frequency synthesizers allowing straightforward noise analysis,” IEEE J. of Solid-State Circuits, vol. 37, no. 8, pp. 1028- 1038, August 2002.
[19] B. De Muer and M. Steyaert, “A CMOS monolithic ΔΣ-controlled fractional-N frequency synthesizer for DCS-1800,” IEEE J. of Solid-State Circuits, vol. 37, no.7, pp.835- 844, July 2002.
[20] E. Sung, et al., “A Wideband 0.18-μm CMOS ΣΔ Fractional-N Frequency Synthesizer with a single VCO for DVB-T,” IEEE Asian Solid- State Circuits Conference, pp.193 - 196, 2005.
[21] S. Saeedi and M. Atarodi., “Single-VCO multi-band DTV frequency synthesizer with a divide-by-3 frequency divider for quadrature signal generation,” Analog Integrated Circuits and Signal Processing, vol. 64, no. 3, pp. 103– 113, August 2010.
[22] W. Lee, J. Cho and S. Lee, “A High Speed and Low Power Phase-Frequency Detector and Charge-pump,” Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 1999.
[23] A. Homayoun and B. Razavi, “Analysis of Phase Noise in Phase/Frequency Detectors,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 3, pp. 529-539, March 2013.
[24] M. Terrovitis, et al., “A 3.2 to 4GHz, 0.25μm CMOS Frequency Synthesizer for IEEE 802.11a/b/g WLAN,” IEEE International Solid State Circuits Conference, ISSCC, 2004.
[25] H. Jalli Ng, et al., “A DLL-Supported, Low Phase Noise Fractional-N PLL With a Wideband VCO and a Highly Linear Frequency Ramp Generator for FMCW Radars,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 12, pp. 3289 - 3302, Dec. 2013.

فایل ها

سابقه مقاله

  • تاریخ دریافت: 26 شهریور 1397
  • تاریخ بازنگری: 13 فروردین 1398
  • تاریخ پذیرش: 18 اردیبهشت 1398
  • تاریخ اولین انتشار: 01 خرداد 1398

اشتراک گذاری

ارجاع به این مقاله

آمار