کاهش توان مصرفی و مقاوم سازی یک جمع کننده در برابر حمله تحلیل توان بر پایه فناوری نوظهور گرافین

نوع مقاله : مقاله پژوهشی

نویسندگان

1 دانشکده مهندسی برق - دانشگاه علوم و فنون هوایی شهید ستاری - تهران - ایران

2 استادیار، گروه مهندسی برق، دانشکده فنی و مهندسی، دانشگاه اردکان، اردکان، ایران.

چکیده

در این مقاله، با کاهش توان مصرفی، برای اولین بار نقش فناوری نوظهور گرافین بر افزایش امنیت در برابر حمله تحلیل توان در مدارهای جمع کننده دیجیتالی بررسی شده است. روش‌های طراحی استاتیک (static) و منطق مد جریانی (CML) برای طراحی جمع کننده‌ها یک، چهار و هشت بیتی در فناوری‌های سیلیکون و گرافین بکار گرفته شده است. در شبیه-سازی برای ترانزیستورهای گرافینی از یک مدل سازگار با SPICE و برای ترانزیستورهای سیلیکونی FINFET از یک مدل PTM استفاده می‌شود. تحلیل نتایج نشان می‌دهد که جمع کننده‌های static مبتنی بر گرافین، کمترین مصرف انرژی را دارند. همچنین تحلیل بالازدگی‌ها و انحراف معیار در دنباله توان یک جمع کننده 8 بیتی تایید می‌کند که جمع کننده CML مبتنی بر گرافین (G-CML) مقاوم‌ترین طرح در برابر حمله تحلیل توان در میان طراحی‌های static و CML است. نهایتا یک روش ترکیبی جدید با ارائه یک مدار پیشنهاد می‌شود که در آن امنیت با ایجاد بینظمی در دنباله توان افزایش یافته است زیرا امکان تشخیص صحیح داده با مشکل مواجه می‌شود. بر این اساس جمع کننده طراحی شده با روش پیشنهادی ضمن کاهش توان مصرفی نسبت به جمع کننده CML، امنیت بالاتری را با ایجاد الگویی متمایز در دنباله توان به همراه دارد.

کلیدواژه‌ها

موضوعات

عنوان مقاله [English]

Lowering Power Consumption and Improving Resistance Against Power Analysis Attack of an Adder with Graphene-Based Emerging Technology

نویسندگان [English]

  • Reza Hooshmand 1
  • Hassan Abdollahi 1
  • Hadi Owlia 2
1 Department of Electrical Engineering, Shahid Sattari Aeronautical University of Science and Technology, Tehran, Iran
2 Faculty of Electrical and Computer Engineering, University of Ardakan
چکیده [English]

In this paper, for the first time, the role of graphene-based emerging technology has been investigated in digital adder circuits. The aims are to decrease power consumption and enhance security against power analysis attack. Static and current mode logic (CML) styles are employed to design one, four, and eight-bit adders in silicon and graphene technologies. In simulations, a SPICE-compatible model for graphene transistors and a PTM model for silicon FINFET transistors are used. Results reveal that the graphene-based static adders show the least power consumption. For an 8-bit adder, power overshoots and standard deviation from power traces confirm that a graphene-based CML (G-CML) adder is the most robust scheme against power analysis attack among the static and CML designs. Eventually, a new hybrid approach is proposed by providing a circuit in which security is enhanced by creating an irregularity in the power trace and this makes the data detection more difficult. Accordingly, an adder based on the proposed approach yield higher security with a different pattern of a power trace and also contains lower power consumption than pure CML-based adders.

کلیدواژه‌ها [English]

  • Secure Low-Power Adder
  • Graphene
  • Graphene FET
  • Current Mode Logic

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سابقه مقاله

  • تاریخ دریافت: 09 بهمن 1397
  • تاریخ بازنگری: 25 مرداد 1398
  • تاریخ پذیرش: 09 آذر 1398
  • تاریخ اولین انتشار: 01 بهمن 1398

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