نویسندگان
1 دانشجوی کارشناسی ارشد برق، دانشگاه صنعتی خواجه نصیرالدین طوسی،
2 استادیار دانشکده برق، دانشگاه صنعتی خواجه نصیرالدین طوسی
چکیده
کلیدواژهها
عنوان مقاله [English]
نویسندگان [English]
In this paper, a fourth-order delta-sigma modulator is designed and simulated. The
presented architecture offers the possibility of implementation of a high-order deltasigma
modulator with multi-bit quantizer without suffering from DAC nonlinearity or
instability problems. The proposed modulator consists of two single-bit second-order
delta-sigma modulators at the first and second stages and an 8-bit pipeline ADC at the
last stage. Besides, a reduced sample rate structure is implemented for the proposed
modulator, which eliminates a few digital filters, and reduces power dissipation.To
prove the idea, both the 2-2-0 MASH delta-sigma-pipeline modulator and its reduced
sample rate counterpart are simulated using MATLAB/SIMULINK. Finally, power
estimation for the proposed ADC at the sampling frequency of 40MHz is presented.
کلیدواژهها [English]