نویسندگان
1 دانشگاه صنعتی اصفهان، دانشجوی دکترای الکترونیک
2 دانشگاه جامع امام حسین (ع)، استادیار
چکیده
کلیدواژهها
عنوان مقاله [English]
نویسندگان [English]
In this paper, a K-band Common-Gate Gilbert-Cell mixer via a 0.18 µm CMOS technology was designed, using the combination of the π-Network and PDC techniques simultaneously, resulting in the improvement of gain, bandwidth, noise figure and linearity. Also, a new method for implementing the π-Network, using the parasitic capacitances between RF and LO stage nodes, is proposed which improves the mixer performance and makes the mixer design possible at high frequencies. The π-Network enhances the gain and bandwidth by generating complex poles in system frequency response without the need for extra power consumption. The suitable location of these poles, which gives rise to high gain and high bandwidth, is discussed and determined by MATLAB simulation. Also, it is shown that these techniques results in a bias-independent mixer circuit at an acceptable range that is a good advantage for circuits. Results of simulation illustrate 3.36dB improvement in power conversion gain and 2dB reduction in noise figure at the same power consumption with LO power of -1 dBm in comparison with the case when PDC technique is used only. Compared to conventional mixer, it improves the IIP3 by 6dB. Also, the power consumption of the mixer together with the designed bias circuit is 9.68 mW at 1.8V.
کلیدواژهها [English]
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