نویسندگان
1 دانشگاه صنعتی نوشیروانی بابل، دکترای کامپیوتر
2 دانشگاه صنعتی نوشیروانی بابل، کارشناس ارشد کامپیوتر
چکیده
کلیدواژهها
عنوان مقاله [English]
نویسندگان [English]
Power consumption is one of the most challenging issues in design of electronic circuits. Reversible logic is a solution for power optimization. In this paper, we propose three fault-tolerant serial multiplier designs based on the reversible logic with error detection capability. The first proposed serial multiplier which is based on the Booth's algorithm utilizes a new arrangement of reversible gates. The second proposed serial multiplier for signed numbers is based on a newer algorithm called the K algorithm. This algorithm requires less cost compared to the Booth's algorithm. The third proposed fault-tolerant serial multiplier which is optimized for unsigned number multiplication is based on the conventional Add & Shift method. The comparative results show that the proposed multipliers are much better than the existing designs considering the main criterions used in reversible logic circuits which include quantum cost, number of gates, number of garbage outputs, delay, and computational complexity.
کلیدواژهها [English]
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