In many applications such as IOT and different parts of the command and controll networks it is essential that information is transferred via network. In applications where the FPGAs are used as processors, due to cost and size limitiation, network layers need to be implemented on FPGA. Also with implementing all layers on FPGA it is possible to encrypt each layer individually. The purpose of this paper presents designing a node in the network based on IEEE802.3 standards so that it can be implemented on FPGA. In this design architecture combination of the data link, network and transport layer is considered. In order to increase speed and reducehe number of used LUTs, the design is based on pipleline. The chosen protocol of the design are IEEE802.3 for the data link layer, IPv4 for network layer and UDP for transport layer. The architecture mentioned above was implemented on xc6slx9-2 chip. Accourding to the results obtained in practice and software synthesise, about 25 percent of the FPGA's logic cells are consumped and 140 Mhz clock speed for the program is obtained.
naderi, A., Darmani, Y., & naseri, A. (2018). Designing layers 3 and 4 of Network on ethernet 10\100 controller core and implementation on FPGA. Electronics Industries, 9(3), 53-60.
MLA
amin naderi; Yousef Darmani; ali naseri. "Designing layers 3 and 4 of Network on ethernet 10\100 controller core and implementation on FPGA". Electronics Industries, 9, 3, 2018, 53-60.
HARVARD
naderi, A., Darmani, Y., naseri, A. (2018). 'Designing layers 3 and 4 of Network on ethernet 10\100 controller core and implementation on FPGA', Electronics Industries, 9(3), pp. 53-60.
VANCOUVER
naderi, A., Darmani, Y., naseri, A. Designing layers 3 and 4 of Network on ethernet 10\100 controller core and implementation on FPGA. Electronics Industries, 2018; 9(3): 53-60.
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