Design of CMOS LNAs with Low Power and Out of Band Rejection Capabilities Using the Improvement of Noise and Linearity in the UWB System

Document Type : Original Article

Authors

1 Electrical & Electronics Engineering , Faculty of Engineering, University of Zanjan

2 Electrical & Electronics Engineering , Faculty of Engineering, University of Zanjan, Zanjan, Iran

Abstract

Noise figure of the Low Noise Amplifier (LNA) is added directly to the system noise figure; therefore, the performance of the Low Noise Amplifiers determines the system's performance in terms of noise. In this paper, Low Noise Amplifiers have been designed in the UWB system, one of them with the ability of out of band rejection and the other with the capability of improving noise and circuit linearity by CMOS technology. In the design of LNA, subthreshold bias technique is used for low power design, chebyshev filtering for matching input impedance and cascode technique to increase inverse isolation and increase gain. In the design of the LNA, using a dual band notch filter which is implemented with low power active inductor, the out of band rejection are improved 42dB at a frequency of 2.4GHz, and 36dB at a frequency of 5.2GHz. Also by using the noise and linearity improvement techniques, 2.3dB reduction in the noise, and 9dB improvement in the circuit linearity (IIP3) is established. The designed LNA,s with a bandwidth of 3 to 5 GHz by using the 0.18 μm CMOS technology, are consumed 2.8mW and 1.9mW from a 1.8V supply voltage, respectively.

Keywords

Main Subjects

References

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Electronics Industries
Volume 10, Issue 2 - Serial Number 38
September 2019
Pages 39-50

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History

  • Receive Date: 04 March 2019
  • Revise Date: 08 June 2019
  • Accept Date: 05 July 2019
  • First Publish Date: 23 August 2019

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