Department of Electrical Engineering, Najafabad Branch, Islamic Azad University, Najafabad, Iran
Abstract
This research aims to optimize a 6-transistor SRAM cell based on combination of Schmitt trigger not gate and force stack methods. Considering previous studies, a 12-transistor circuit; single-ended is proposed with 22nm technology at voltage 0.5 volt. There is an opportunity to use this circuit as a Force stack in hold state and in reading mode the cell will be single ended ,So Schmitt trigger not gate will inter the circuit, prevents the reading error. The purpose of this study is to optimize the parameters including speed, power and static noise margin. Finally, the effects of replacing CNTFET transistors on parameters has been investigated using simulation. Simulations have been performed by Hspice software at 25°C. Simulation results have shown that the suggested circuit based on CNTs, increases HSNM about 214mV due to using force stack method. Also, in reading mode RSNM increases more than 131mV considering the not Schmitt trigger’s gate. Since Nano-tube transistors were used, leakage power decrease from nW to pw and circuit’s delay is optimized.
amoon, M., & norouzi, A. (2021). 12T SRAM memory cell, based on CNTFET with 22nm channel length consist of Schmitt-Trigger. Electronics Industries, 12(1), 53-62.
MLA
mehdi amoon; ali norouzi. "12T SRAM memory cell, based on CNTFET with 22nm channel length consist of Schmitt-Trigger". Electronics Industries, 12, 1, 2021, 53-62.
HARVARD
amoon, M., norouzi, A. (2021). '12T SRAM memory cell, based on CNTFET with 22nm channel length consist of Schmitt-Trigger', Electronics Industries, 12(1), pp. 53-62.
VANCOUVER
amoon, M., norouzi, A. 12T SRAM memory cell, based on CNTFET with 22nm channel length consist of Schmitt-Trigger. Electronics Industries, 2021; 12(1): 53-62.
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