In this paper, a fourth-order delta-sigma modulator is designed and simulated. The
presented architecture offers the possibility of implementation of a high-order deltasigma
modulator with multi-bit quantizer without suffering from DAC nonlinearity or
instability problems. The proposed modulator consists of two single-bit second-order
delta-sigma modulators at the first and second stages and an 8-bit pipeline ADC at the
last stage. Besides, a reduced sample rate structure is implemented for the proposed
modulator, which eliminates a few digital filters, and reduces power dissipation.To
prove the idea, both the 2-2-0 MASH delta-sigma-pipeline modulator and its reduced
sample rate counterpart are simulated using MATLAB/SIMULINK. Finally, power
estimation for the proposed ADC at the sampling frequency of 40MHz is presented.
a, A., & b, A. (2012). Noise Shaping, Delta-Sigma Modulator, Pipeline Analog-to-Digital Convertor,
Oversampling Ratio. Electronics Industries, 3(4), 7-28.
MLA
a a; a b. "Noise Shaping, Delta-Sigma Modulator, Pipeline Analog-to-Digital Convertor,
Oversampling Ratio". Electronics Industries, 3, 4, 2012, 7-28.
HARVARD
a, A., b, A. (2012). 'Noise Shaping, Delta-Sigma Modulator, Pipeline Analog-to-Digital Convertor,
Oversampling Ratio', Electronics Industries, 3(4), pp. 7-28.
VANCOUVER
a, A., b, A. Noise Shaping, Delta-Sigma Modulator, Pipeline Analog-to-Digital Convertor,
Oversampling Ratio. Electronics Industries, 2012; 3(4): 7-28.
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