This paper examines the effects of operating point and device size on the high frequency noise parameters in CMOS technology, to eliminate high power dissipation challenge in simultaneous noise and input matching (SNIM) technique. Modified technique is applied to improve power dissipation problem, noise performance, gain and input/output matching of the LNA at center frequency of 5.2 GHz. The LNA is implemented in TSMC 0.18-µm CMOS process. Post-layout simulation results demonstrate LNA has reached to power consumption of 2.1 mW under 1.4 V supply while having, 2.71 dB noise figure, 1GHz Band-width, 16.38 dB power gain, -40.42 dB reverse isolation factor, -21.5 dB and -23.59 dB input/output return loss respectively.
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