This paper presents a low-dropout regulator (LDO) based on the flipped voltage follower (FVF) in which an external feedback loop is used to improve the static performance of the circuit. Moreover, due to the possibility of eliminating the off-chip output capacitor, the proposed LDO can be fully integrated. Also, decreasing the power dissipation of the LDO circuit in comparison to other similar architectures, make it suitable for low power applications. It is shown that the proposed LDO has a perfect dynamic performance in addition to the load and line regulations while it consumes only 31 μA quiescent current. Simulation results are done in HSPICE in a 0.35 μm CMOS process.
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