نوع مقاله : مقاله پژوهشی
نویسندگان
گروه برق، دانشکده فنی، دانشگاه گیلان
چکیده
کلیدواژهها
عنوان مقاله [English]
نویسندگان [English]
This paper presents an 8-bit analog-to-digital converter (ADC) designed using an improved successive approximation Register(SAR). The proposed structure of the SAR converter uses an integrator embedded with a digital-to-analog converter (DAC). The presence of an integrator at the input of the ADC eliminates the need for a sample and hold circuit and is used to generate different voltage levels in the DAC. Thus, the successive approximation algorithm in the proposed structure has been modified to provide the required voltage levels with a few number of capacitors in the DAC. Therefore, the complexity of the circuit is reduced and less silicon is occupied due to a reduced capacitive array in DAC. The proposed ADC completes the analog input to digital code conversion in 10 clock pulses. In order to study the proposed method, the SAR ADC is designed and simulated at the transistor level in 0.18 μm CMOS technology at 1.8 V supply voltage. The simulation results show that the ratio of signal to noise and distortion (SNDR) for input bandwidth of 640 kHz is 48.3 dB, effective number of bit (ENOB) and power consumption are 48.3 dB, 7.74 bits and 0.85 mW, respectively.
کلیدواژهها [English]
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