نویسندگان
دانشگاه تربیت مدرس
چکیده
کلیدواژهها
عنوان مقاله [English]
نویسندگان [English]
In this paper, hardware implementation of an LDPC decoder for WiMAX Standard has been presented.
The parity-check matrix (H) for the codes of this standard with length of 2304 and rate of 5/6 with long
girth has been designed through the encoder model matrix. For efficient implementation, the matrix H
has been considered as QC-LDPC structure. The Offset-Min-Sum (OMS) algorithm as an optimum
decoding algorithm is used for implementation with its calculated β parameter. Also for solving the
memory multi-access problem in semi-parallel implementation, a new method has been proposed that
based on it and using the message overlapping methods, the decoder speed has been improved. The
decoder is initially implemented on a FPGA chipset through Verilog hardware description language and
finally it is synthesized with 0.13uCMOS TSMC process through the Synopsis-Design-Complier
package.
کلیدواژهها [English]
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